1. Technical Field
Various embodiments relate to a semiconductor system, and more particularly, to a semiconductor system which is constituted by a master chip and a slave chip.
2. Related Art
In order to increase the capacity and the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus which includes a plurality of chips stacked and packaged in a single package has been developed. Recently, a through-silicon via (TSV) method has been used, in which a plurality of stacked chips are electrically coupled through TSVs.
FIG. 1 is a diagram schematically showing the configuration of a conventional semiconductor apparatus 10. In FIG. 1, the semiconductor apparatus 10 includes a master chip 11 and a plurality of slave chips 12. The master chip 11 may communicate with a host device and receive signals for controlling the respective slave chips 12. The master chip 11 may provide the signals received from the host device, to the slave chips 12, and may receive the data which are outputted from the slave chips 12.
The master chip 11 and the plurality of slave chips 12 may be stacked through through vias 13, 14, 15 and 16 and bumps 17. The through vias 13 and 14 of the slave chips 12 are electrically coupled in series and form data channels. The first through vias 13 of the slave chips 12 may form a first data channel DQ1, and the second through vias 14 of the slave chips 12 may form a second data channel DQ2. The slave chips 12 may include increased numbers of through vias and may be formed with increased numbers of data channels. The third through vias 15 may form a command channel CMD, and the slave chips 12 may receive a command signal through the command channel CMD from the master chip 11. The fourth through vias 16 may form an address channel ADD, and the slave chips 12 may receive an address signal through the address channel ADD from the master chip 11. The slave chips 12 may receive the command signal and the address signal from the master chip 11 and may output stored data to the master chip 11 through the first and second data channels DQ1 and DQ2. In this way, the slave chips 12 share the data channels DQ1 and DQ2, the command channel CMD and the address channel ADD.
Since it is difficult for the slave chips 12 constituting the semiconductor apparatus 10 to be manufactured under perfectly the same processing conditions, the slave chips 12 cannot help but have processing skews. For example, in the case where a lowermost stacked slave chip has an earliest processing skew and an uppermost stacked slave chip has a latest processing skew, times from when the master chip 11 provides the command signal to the slave chips 12 to when data are received from the respective slave chips 12 may have substantial errors. These errors may serve as factors that degrade the operation performance of the semiconductor apparatus.